Electroless plating is a method used to deposit a thin film or a layer of some material on a substrate. The principal step is the immersion of the substrate in a plating bath containing ions of the material to be deposited, causing some of these ions to precipitate at the substrate's surface. Unlike electroplating methods, electroless plating does not require an externally applied electric field to facilitate the ion deposition process. The electroless plating may be selective, i.e., the deposition may occur only at locations that exhibit appropriate electrochemical properties. For example, the ions may be deposited mainly on those portions of the substrate that are made of a material identical (or exhibiting affinity) to the material being deposited. Another of many possibilities is that portions of the substrate may be treated or activated with a catalyst to cause the ion deposition to occur at a rapid rate. The material or catalyst present in the selected areas before the deposition is sometimes referred to as "seed material" or "seed layer". The ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is referred to as the "plating process selectivity." The deposition rate may also depend on the physical characteristics of the activated areas, e.g., their sizes, aspect ratios, and distances separating them. If the thickness of the material deposited in various locations at the substrate is similar, the plating process is said to be uniform. For many applications, it is crucial that the plating process be uniform, that it exhibit high selectivity, and that the deposited film strongly adheres to the substrate. The adhesion is commonly measured with a "scotch tape" test, where adhesion is deemed acceptable if a piece of a "scotch tape" can be pressed onto the plated surface and lifted off without destroying any plated features. One of the ways to increase the adhesion is to subject the plated artifact to an annealing process. The conditions or process parameters such as the temperature, ion concentration in the plating path, and duration of the bath, which provide desirable uniformity, selectivity, and some physical properties of the deposited layer usually fall within certain ranges, the combination of which is called a "technological process window." To ensure the repeatability and consistency of the plating process, it is desirable that the process window be as large as possible.
Electroless plating of solid metals from a solution containing metal ions onto a catalytically active surface has been widely used in the printed circuit board industry for production of wiring layers and inter-layer (via) connections. More recently, this body of knowledge has been applied to producing metal interconnect films in the integrated circuit (IC) industry. The electroless plating technique has several advantages over other well known metal deposition techniques such as sputtering and evaporation. One advantage is that the electroless plating process uses materials and capital equipment that are inexpensive compared to the other methods. Another advantage is that the technique deposits films only in selected, catalytically active regions. This property of selective growth allows the user to reduce the number of lithographic patterning and etching steps used to define the regions to be covered by the deposited metal. It also facilitates dense patterning of materials such as copper, that are difficult to etch anisotropically . Yet another advantage is that the growth rate of the deposited metal is relatively independent of the angles or relative heights of topographic features on the substrate being plated. This property enables deposition into features having high aspect ratios, such as deep via holes on multi-layer circuit boards, that could not be uniformly covered by the "line of sight" deposition techniques such as sputtering and evaporation.
The most commonly published use of electroless plating in the integrated circuit industry is for filling contact or via holes. The traditional contact is a hole, patterned and etched in a dielectric film placed on top of a conducting film so that the surface of the conducting film is exposed within the hole. An upper level of conductor, patterned over the contact hole, makes a physical and electrical contact with the lower conductor in the contact region. Electroless plating has been used to grow metal selectively onto the surface of the lower conductor that is exposed in the contact hole. This produces a metallic "plug" which electrically couples the upper conductor to the lower conductor. The "plug" is plated until its top surface substantially coincides with the top surface of the dielectric, and the resulting planarity of the structure prevents problems that might occur in the subsequent processing if topographic variations were present in the vicinity of the contact region.
Although electroless plating-based processes, such as contact-hole filling, offer many advantages to the process designer, the technique has only found limited acceptance within the IC manufacturing community. Although the technique appears to be relatively simple, the chemical reactions occurring at the plated surface can be complex. Some of the factors inhibiting the wider application of electroless plating are the difficulties in controlling the plating process and in obtaining uniform plating thickness on the entire substrate, as well as the sensitivity to contaminants exhibited by the process. Many of these problems are related to the previously known surface activation techniques, i.e., methods used to render the plated surface catalytically active. The present invention teaches a new surface preparation technique that provides a more active surface on which to plate, thereby improving the latitude of the plating process and the uniformity of the plated materials.
Many surface activation techniques have been reported in both the patent and scientific literature. Frequently, these techniques are designed for plating a specific material onto a specific substrate material, and rely on certain properties of these materials.
The most common applications of electroless plating to integrated circuit manufacturing comprise plating of nickel, cobalt, palladium, or copper onto one of two types of substrate surfaces. The first type of substrate surface comprises conductive regions of substrates that are generally formed of silicon, aluminum, or aluminum alloys. The second type of substrate comprises a non-conductor such as silicon dioxide or a polymeric insulator The reported surface activation techniques applied to these substrates usually fall into one of three categories: (1) catalyst film deposition by evaporation or sputtering, (2) catalyst film deposition by electrochemical surface modification, and (3) catalytic film deposition from a colloidal suspension.
Palladium and platinum are frequently used as catalytic surface activators in electroless plating methods. Catalytic films of palladium or platinum for subsequent electroless plating can be readily deposited by evaporation or sputtering techniques (Harada et al., J. Electrochem. Soc., November 1986, p. 2428). The films deposited with these techniques can be patterned by well known lithographic techniques, e.g., subtractive etching or liftoff. Large features and/or dense patterns of small features are relatively easy to plate with this method. U.S. Pat. No. 4,182,781 teaches a method to fabricate elevated metal bumps on aluminum bonding pads. In accordance with this method, a palladium film is deposited and patterned on the upper surface of an aluminum wiring layer on an integrated circuit. An insulating layer is deposited over the surface of the substrate and patterned to provide holes exposing the palladium film surface in regions where elevated metal bumps are desired. The substrate is then immersed in an electroless plating bath, resulting in a deposition of metal features that are self-aligned to the apertures opened in the insulating film. While this technique is effective for fabricating the relatively large features discussed in the patent, the palladium film disclosed appears not to provide sufficient catalytic activity to enable plating of the small features commonly fabricated in modern integrated circuit manufacturing, particularly if those small features are located far away from other plated features.
It has been reported that the catalytic activity of palladium films deposited by evaporation and sputtering is lower than that of palladium films deposited by other techniques, for example electrochemically deposited films. This low activity has a significant detrimental impact on the uniformity of structures formed by this process and on the resulting yield. (Svendsen, et al., J Electrochemical. Soc., November 1983, p 2252, and Osaka et al., J. Electrochem. Soc., September 1983, p. 2081) Features that are small or separated with large distances from other features are significantly more difficult to plate. These size-dependent and proximity-dependent effects are often related to the presence of stabilizing agents (stabilizers) in the plating solutions. Stabilizers are added to most commercially available plating solutions to prevent the spontaneous decomposition of the plating bath. Generally, the stabilizers reduce or even prevent the auto-catalytic plating reaction from occurring on small particles that may be present in the bath. The presence of such particles may result from a contamination of the plating bath with the airborne dust. The stabilizing agents also exert a significant and beneficial impact on the electrical and mechanical properties of the deposited film, although the mechanisms for this action are not always clearly understood. It is intuitively clear, however, that any mechanism that prevents undesirable auto-catalytic plating on small particles in the bath may also impede the desirable plating of small, isolated features present on the substrate. Plating of small features may be enhanced by modifying the bath composition or process conditions. For instance, the ability to plate sub-micrometer features can be improved by raising the plating bath temperature, or by reducing the amount of the stabilizing agents in the bath. This improvement is obtained the price of a reduced plating selectivity and reduced bath stability.
The plating non-uniformity and process selectivity also depend on the detailed history of the catalytic surface. Subjecting this surface to any post-patterning clean-up processes or exposing it to air before plating reduce the ability to uniformly plate the desired features. U.S. Pat. No. 5,127,986 discloses the placement of a protective chromium film, that is deposited over a palladium catalyst film. The chromium has two beneficial effects: (1) the adhesion of the dielectric offer the areas comprising the seed metal covered with the catalyst and chromium films is increased compared to the adhesion of the same dielectric to the seed metal covered by the catalyst film only, and (2) the chromium film shelters the palladium catalyst from the adverse effects of some processes to which the substrate is subjected before plating. The chromium film can be removed by etching it immediately prior to the plating process, thus reducing the exposure of the catalyst to oxidation or other process-induced degradation. Direct comparisons of this technique to those using electrochemically deposited catalysts, and to the present invention, demonstrate that the use of a protective layer only provides a fresh surface upon which to plate. The catalytic activity of this surface is similar to a freshly deposited palladium film and is significantly lower than that provided by other techniques, including the present invention.
A wide range of electrochemical surface modification techniques to enable the catalytic plating on metallic and dielectric materials have been disclosed. As disclosed in U.S. Pat. No. 5,169,680, aluminum films used in VLSI circuits can be rendered catalytically active by electroless plating of a seed layer of palladium from a bath containing a dilute aqueous solution of PdCl.sub.2 and HCl. Typically, the pre-existing aluminum oxide is removed by a short immersion in a dilute HF solution prior to the palladium activation. The degree of activation achieved by this technique depends strongly on the processing history of the aluminum surface, the concentration of the activator components, the temperature, and duration of the exposure of the aluminum surface to the activator. This method can achieve very high levels of activation, but suffers from a very small "process window" . If the exposure to the activator solution is too brief, the insufficient surface activation and the resulting plating non-uniformity will occur. If the exposure to the activator solution is too long, the plated metal will exhibit poor adhesion. While this process has been demonstrated to work, the development of a stable, reproducible manufacturing implementation is difficult. Using a similar technique, U.S. Pat. Nos. 4,122,215 and 4,125,648 teach a similar method of activating aluminum surfaces by contact of the aluminum with a solution containing nickel ions.
U.S. Pat No. 4,372,996 illustrates another method of activating aluminum surfaces using the electroless deposition of zinc. The zinc is then used as a catalytic seed material for subsequent plating of the nickel film. This process is commonly refereed to as "zincating", and is extremely effective for activating larger dimension patterns but suffers from a reduced process window in the presence of features with small dimensions, such as used in many integrated circuits. The process exhibits a tradeoff between activation and adhesion similar to the one discussed above for palladium-based activation.
Several techniques have been disclosed that use alloys of palladium to seed electroless plating. Copper deposition from a thermally grown film of palladium silicide was discussed in Mak, et. al., Appl. Phys. Letters, 59, December 1991. U.S. Pat. No. 5,098,526 discloses selective plating in regions where a reaction between a palladium film and a dielectric film deposited over it is induced with a high-energy laser. U.S. Pat. No. 4,746,375 teaches the method of activating refractory metals by a high-temperature exposure to a carburizing atmosphere.
A significant amount of prior art is directed toward the modification of dielectric surfaces to enable electroless plating onto the modified material. U.S. Pat. Nos. 3,650,913, 3,976,816, 4,132,832, 4,220,678, 4,258,087, 4,261,747, 4,278,712, 4,282,271, 4,317,846, 4,318,940, 4,323,594, and 4,863,758 all discuss variants of the widely known method consisting of exposure of a non-conducting surface to a medium containing dispersed catalytic particles. Many of these patents teach various methods of making and using solutions containing tin and palladium ions or colloidal dispersions of tin-palladium particles. U.S. Pat. No. 4,042,730 teaches the activation of dielectric surfaces by sequential exposure to tin- and palladium-containing baths. U.S. Pat. No. 5,108,553 activates a dielectric surface by contact to a dispersion of carbon particles and U.S. Pat. No. 4,910,049 uses semiconductor particles that are laminated onto the dielectric. Yet another approach involves chemical treatment of dielectric polymer surfaces to render them catalytically active. This approach is taken by the authors of U.S. Pat. Nos. 4,078,096, 4,112,139, 4,910,045, 5,135,779, 5,165,971, and 5,160,600. U.S. Pat. No. 5,183,795 discloses the novel technique for the patterned activation of silicon dioxide that has been implanted with catalytically active ions.